In high resolution digital-to-analog converters (DACs), performance metrics such as linearity and noise are nominally determined by the matching of parameters derived from physical quantities in the construction of the DACs on an integrated circuit (IC), such as width, length, thickness, doping, etc. As a general rule, for each additional bit of performance in the DAC, parameter matching needs to be twice as tight. This translates to an increase by a factor of four in the IC area required by the DAC. When the DAC resolution is in the 16-bit range, it is no longer practical/economical to use size alone to achieve the required matching.
Over-sampled (sigma-delta) DACs (also referred to as “converters”) alleviate the need for raw matching using single-bit conversion (so called 1-bit DACs in CD players). A single-bit DAC has only two points in a transfer function of the DAC, and thus is inherently linear. The function of a sigma-delta modulator with a one-bit quantizer is to approximate a high resolution low frequency signal with a high frequency two-level signal. The drawback here is this produces large amounts of out-of-band, for example, high frequency, noise.
One solution is to use more than two levels of quantization. For example, 17 levels may be used. However, now linearity requirements are to the full resolution of the DAC. That is, for a 16-bit DAC, the transfer function of the DAC with these quantization levels must be collinear to 1 part in 216, which is 1 part in 65,536. Such linearity is difficult to achieve with raw parameter matching of the single-bit DACs. Thus, there is need to achieve such linearity in a multi-level DAC using an alternative to raw parameter matching.